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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance
PHP42N03LT, PHB42N03LT
SYMBOL
d
QUICK REFERENCE DATA VDSS = 30 V ID = 42 A
g
RDS(ON) 26 m (VGS = 5 V) RDS(ON) 23 m (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP42N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB42N03LT is supplied in the SOT404 surface mounting package.
PINNING
PIN 1 2 3 tab gate drain 1 source drain DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C; VGS = 5 V Tmb = 100 C; VGS = 5 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 30 30 15 42 30 168 86 175 UNIT V V V A A A W C
November 1998
1
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS
PHP42N03LT, PHB42N03LT
MIN. -
TYP. MAX. UNIT 60 50 1.75 K/W K/W K/W
SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint
-
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175C Forward transconductance VDS = 25 V; ID = 25 A Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175C Gate source leakage current VGS = 5 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 20 A; VDD = 24 V; VGS = 10 V MIN. 30 27 1 0.5 8 TYP. MAX. UNIT 1.5 16 20 27 0.05 10 40 7 10 12 80 35 31 3.5 4.5 7.5 1050 270 140 2 2.3 23 26 48 10 500 100 20 130 60 45 V V V V V m m m S A A nA nC nC nC ns ns ns ns nH nH nH pF pF pF
VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Resistive load Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
November 1998
2
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP42N03LT, PHB42N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 40 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 25 V TYP. MAX. UNIT 0.95 1.0 52 0.08 45 180 1.2 A A V ns C
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1000
ID, Drain current (Amps)
PHP42N03LT
100
RD
S
) (ON
=V
DS
/ID
tp = 10us 100 us 1 ms DC 10 ms 100 ms
10
0
20
40
60
80 100 Tmb / C
120
140
160
180
1
Tmb = 25 C 1 10 VDS, Drain-source voltage (Volts) 100
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Normalised Current Derating
Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth j-mb / (K/W) D=
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
10
7528-30
1 0.5 0.2 0.1 0.1 0.05 0.02 0
0 20 40 60 80 100 Tmb / C 120 140 160 180
P D
tp
D=
tp T t
0.01 1E-07
T
1E-05
1E-03 t/s
1E-01
1E+01
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
November 1998
3
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP42N03LT, PHB42N03LT
80 70 60 50 40 30 20 10 0
ID, Drain current (Amps) 15 V 5V 10 V
PHP45N03LT Tj = 25 C 4.5 V
30 25
Transconductance, gfs (S) VDS = 25 V Tj = 25 C
PHP45N03LT
4V
20 175 C 15 10
3.5 V 3V
5
VGS = 2.5 V 0 2 4 6 8 VDS, Drain-Source voltage (Volts) 10
0
0
10
20 30 Drain current, ID (A)
40
50
Fig.5. Typical output characteristics ID = f(VDS); parameter VGS
Drain-Source on resistance, RDS(on) (Ohms) 3V 3.5 V 4V 4.5 V
Fig.8. Typical transconductance gfs = f(ID)
a 2
0.06 0.05
30V TrenchMOS
1.5
0.04 0.03 0.02 0.01 Tj = 25 C 0 0 10 20 30 40 50 ID, Drain current (Amps) PHP45N03LT 60 70 80
5V 10 V VGS = 15 V
1
0.5
0 -100
-50
0
50 Tj / C
100
150
200
Fig.6. Typical on-state resistance RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj)
VGS(TO) / V max. BUK959-60
50
Drain current, ID (A) VDS = 25 V
PHP45N03LT
2.5
40
2 typ.
30
1.5 min.
20
1
10 175 C 0 0 1 Tj = 25 C 5 6
0.5
2 3 4 Gate-source voltage, VGS (V)
0 -100
-50
0
50 Tj / C
100
150
200
Fig.7. Typical transfer characteristics. ID = f(VGS)
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
November 1998
4
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP42N03LT, PHB42N03LT
1E-01
Sub-Threshold Conduction
15
VGS, Gate-Source voltage (Volts)
VDD=24V ID=20A Tj = 25C
PHP50N03LT
1E-02
10
1E-03
2%
typ
98%
1E-04
5
1E-05
0 0 10 20 30 Qg, Gate charge (nC) 40 50
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current. ID = f(VGS); VDS = VGS
C / pF
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
IF / A 9528-30
10000
9528-30
60 50 40
Tj / C = 175
25
1000
Ciss
30 20
Coss Crss 100 0.1 1 VDS / V 10 100
10 0
0
0.5
1 VSDS / V
1.5
2
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); VGS = 0 V; f = 1 MHz
Fig.14. Typical reverse diode current. IF = f(VSDS)
November 1998
5
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
PHP42N03LT, PHB42N03LT
4,5 max 10,3 max
1,3
3,7 2,8
5,9 min
15,8 max
3,0 max not tinned
3,0
13,5 min
1,3 max 1 2 3 (2x)
2,54 2,54
0,9 max (3x)
0,6 2,4
Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8".
November 1998
6
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 1.4 g
10.3 max
PHP42N03LT, PHB42N03LT
4.5 max 1.4 max
11 max 15.4
2.5 0.85 max (x2) 2.54 (x2)
0.5
Fig.16. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5 2.0
3.8
5.08
Fig.17. SOT404 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
November 1998
7
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHP42N03LT, PHB42N03LT
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
November 1998
8
Rev 1.400

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